Design Verification Engineer

Job opening at Hyderabad

Location

Hyderabad

Address

Hyderabad

Employment

Full Time

Qualification

Any Graduate

Payment

400000 to 5000000

Date Posted

2025 May,30

HR

Shubhangini Nag

Contact

shubhangini.whiteforce2@gmail.com

Mobile

6264800164


Job description




























































Normal
0




false
false
false

EN-US
X-NONE
HI































































































































































































Position: Design Verification
Engineer (SoC, SystemVerilog /UVM)







Location: Serillingampalli ,
Hyderabad


















Job
Description:







We are seeking a talented and
motivated Design Verification Engineer to join our hardware development
team. You will be responsible for verifying complex SoC designs using
industry-standard methodologies such as SystemVerilog and UVM
(Universal Verification Methodology)
. The ideal candidate will have a solid
background in digital design verification, strong problem-solving skills, and
hands-on experience with SoC architectures.


















Key
Responsibilities:








  • Develop and execute detailed verification plans
    based on design specifications and architecture documents.

  • Build UVM-based testbenches to verify RTL at
    block, subsystem, and SoC levels.

  • Create and maintain test cases to achieve functional
    coverage and code coverage goals.

  • Debug failures using waveform viewers and simulation
    logs; work with RTL designers to resolve issues.

  • Integrate third-party IPs and verify their correct
    integration into the SoC.

  • Perform coverage analysis and drive verification
    closure.

  • Contribute to verification methodology and automation
    enhancements.


















Required
Skills and Experience:








  • Bachelor's or Master’s degree in Electrical
    Engineering
    , Computer Engineering, or related field.

  • 12+ years
    of hands-on experience in digital design verification.

  • Strong experience with SystemVerilog and UVM
    methodology
    .

  • Solid understanding of SoC architecture,
    including buses like AXI, AHB, and interfaces such as PCIe, USB, or
    Ethernet.

  • Familiarity with code and functional coverage,
    constrained random testing, assertions (SVA), and checkers.

  • Proficiency with simulation tools (e.g., Synopsys
    VCS
    , Cadence Xcelium, Mentor Questa).

  • Strong debugging skills with waveform tools (e.g., DVE,
    SimVision, Verdi).

  • Experience working in Linux-based environments
    with scripting (Python, Perl, or shell).




























Thanks and Regards
Sakshee Khampariya
9201975264


Job requirements

  • Experience: 6 to 20 Year.
  • Education : Any Graduate
  • Specilization : B.Tech...
  • Skills :
    1 SOC
    2 designverification
    3 SV
    4 UVM
  • Industry Type : IT-Software / Software Services
  • Status : Not Disclose.

Company Name : Modernize Chip Solutions

Website

About Company

Modernize Chip Solutions is one of the fastest-growing semiconductor services company Read more