We are seeking a talented and
motivated Design Verification Engineer to join our hardware development
team. You will be responsible for verifying complex SoC designs using
industry-standard methodologies such as SystemVerilog and UVM
(Universal Verification Methodology). The ideal candidate will have a solid
background in digital design verification, strong problem-solving skills, and
hands-on experience with SoC architectures.
Key
Responsibilities:
Develop and execute detailed verification plans
based on design specifications and architecture documents.
Build UVM-based testbenches to verify RTL at
block, subsystem, and SoC levels.
Create and maintain test cases to achieve functional
coverage and code coverage goals.
Debug failures using waveform viewers and simulation
logs; work with RTL designers to resolve issues.
Integrate third-party IPs and verify their correct
integration into the SoC.
Perform coverage analysis and drive verification
closure.
Contribute to verification methodology and automation
enhancements.
Required
Skills and Experience:
Bachelor's or Master’s degree in Electrical
Engineering, Computer Engineering, or related field.
12+ years
of hands-on experience in digital design verification.
Strong experience with SystemVerilog and UVM
methodology.
Solid understanding of SoC architecture,
including buses like AXI, AHB, and interfaces such as PCIe, USB, or
Ethernet.
Familiarity with code and functional coverage,
constrained random testing, assertions (SVA), and checkers.