Position name: VHDL FPGA Engineer Team member Educational Qualification: BE/B. Tech in ECE/EEE/EIE/CSE (Other degree profiles will be rejected directly) Location: Bangalore & Hyderabad (Initially, the project will start at the Bangalore location. Later, the project may start in Hyderabad. The candidate should be OK for both locations.) Budget: 7-9 LPA LPA Joining: Within 15-20 days Others: Candidate should be ready for a 2-year signed commitment with Oak Systems. Experience : Minimum 02 Years of post-qualification experience in: Job Description Design / development / verification & validation of RTL or IP cores for FPGA based embedded systems Experience on Position name: VHDL FPGA Engineer Team member Educational Qualification: BE/B. Tech in ECE/EEE/EIE/CSE (Other degree profiles will be rejected directly) Location: Bangalore & Hyderabad (Initially, the project will start at the Bangalore location. Later, the project may start in Hyderabad. The candidate should be OK for both locations.) Budget: 7-9 LPA LPA Joining: Within 15-20 days Others: Candidate should be ready for a 2-year signed commitment with Oak Systems. Experience : Minimum 02 Years of post-qualification experience in: Job Description Design / development / verification & validation of RTL or IP cores for FPGA based embedded systems Experience on FPGA based embedded system based on Xilinx/Altera/Actel etc RTL Design, experience in VHDL, Verilog HDL VHDL coding, logic synthesis and verification. Desirable: Experience in: Vivado/Libero design suite, Mentor Graphics/Aldec V&V tools Ability to write test benches for FPGA based design validation Kindly revert me with your updated CV Desirable: Experience in: Vivado/Libero design suite, Mentor Graphics/Aldec V&V tools Ability to write test benches for FPGA based design validation Kindly revert me with your updated CV
